It is well known to construct a first-in first-out (FIFO) buffer or memory array that reads various size data words. The prior art required a shift register scheme to generate a number of intermediate signals necessary to incorporate a fixed word width data pack into the memory array. To implement a clocking scheme that stores fixed width data words that are equal to the width of the individual cells in the FIFO buffer, a 16-bit multiplexer would be required. To extend the prior art scheme to a memory array that is twice as wide as the width of the input data word, a 32-bit shift register would be required. Specifically, a 32-bit shift register would be necessary for a 9-bit word design and a 6-bit shift register would be required for a 18-bit word design. The prior art did not allow a single decode block to be used for both the 9-bit and 18-bit devices. The prior art FIFO's used a "carousel" type data placement scheme that used a 16-bit shift register to directly control each of the section signals. To extend the prior art system to decode both a 9-bit and 18-bit word would require a 32-bit shift register. The implementation of a 32-bit shift register would cause extreme difficulty in routing the various signals to appropriately connect the outputs of the shift register to each of the section control blocks. The implementation of a 32-bit shift register would also consume more than twice the amount of chip area that a 16-bit shift register would consume.
Referring to FIG. 1, a prior art scheme is shown generally comprising a shift register 12, a set of multiplexers 14a, 14b, 14c and 14d and a set of memory arrays 16a, 16b, 16c and 16d. A single data input 18 presents an input to each of the multiplexers 14a-d. The 16-bit shift register 12 presents one of a set of control inputs 20a, 20b, 20c and 20d to each of the multiplexers 14a-d. When the control input 20a-d is present at the multiplexer 14a-d, the data input 18 is received and is presented to the appropriate memory array 16a-d. An individual control input 20a-d is required for each memory array 16a-d. As the number of memory arrays 16a-d increases, the number of control inputs 20 will also increase. Each of the select inputs 20a-d would need to be individually routed from the individual multiplexers 14a-d to the shift register 12. The routing necessary to appropriately connect the control inputs 20a-d between the shift register 12 and the multiplexers 14a-d increases. To expand the shift register 12 to a 32-bit shift register would require twice the amount of routing as well as an increased amount of chip real estate to implement the shift register 12. The increase in routing the control inputs 20a-d and the increased chip area makes the prior art scheme difficult to implement with multiple width data words.